The present application claims the benefit of Korean Patent Application No. 2002-0088488 filed in Korea on Dec. 31, 2002, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an array substrate for use in liquid crystal display devices, and more particularly, to an array substrate having multiple cells and an array testing system implanted thereon.
2. Discussion of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite alignment orientation due to their long, thin shapes. The alignment orientation can be controlled by application of an electric field. Accordingly, the alignment of the liquid crystal molecules can be altered by changing the applied electric field. Due to the optical anisotropy of the liquid crystal molecules, refraction of incident light is dependent upon the orientation of the aligned liquid crystal molecules. Therefore, by controlling the electric field applied to the liquid crystal molecules, an image can be produced by the liquid crystal display device.
Liquid crystal display (LCD) devices have wide application in office automation (OA) and video equipment because of their light weight, thin design, and low power consumption characteristics. Among the different types of LCD devices, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, offer high resolution and superiority in displaying moving images. A typical LCD panel has an upper substrate, a lower substrate and a liquid crystal material layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs), and pixel electrodes, for example.
As previously described, operation of an LCD device is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an applied electric field between the common electrode and the pixel electrode. Accordingly, the liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
When fabricating the liquid crystal panel, a first substrate (i.e., lower substrate or array substrate) and a second substrate (i.e., upper substrate or color filter substrate) are previously fabricated and then bonded and aligned to each other. Thereafter, liquid crystal material is interposed between the first and second substrates. Then, the attached substrates are divided into individual liquid crystal cells.
The fabrication process for the first substrate includes many thin film deposition processes to form insulating layers, semiconductor layers and conductive layers, as well as many etching and/or patterning processes to form desired layer patterns, thereby forming a plurality of thin film transistors, pixels and other layer elements. At this time of manufacturing the first substrate, a plurality of array cells each including the plurality of thin film transistors and array elements are formed on a large substrate to decrease fabrication process steps. In such a manner, a plurality of color filter cells each corresponding to each array cell are formed on a large substrate that is for the second substrates of the liquid crystal display panel. Those two large substrates respectively having the plurality of array cells and color filter cells are attached to each other with the liquid crystal layer interposed therebetween, thereby forming the liquid crystal display panel. Thereafter, the attached liquid crystal panel is cut and divided into the liquid crystal cells.
Before attaching the two large substrates, the large first substrate (array substrate) is tested by an array testing system to analyze whether the large array substrate has any defects. The large first substrate is often called as an array testing substrate because this substrate has many array cells for the array test with a plurality of test pads and test lines.
FIG. 1 is a plan view illustrating an array testing substrate having a plurality of array cells according to the related art. FIG. 2 is an enlarged plan view of an array cell of FIG. 1 and array cells adjacent thereto.
As mentioned before, the array substrate for the array test includes a plurality of array cells 10. Each array cell 10 has divided regions of a display area 20, a non-display area 30 and a pad area 40. The display area 20 includes a plurality of pixels P each having a thin film transistor T to show images. The non-display area 30 is disposed surrounding the display area 20. The pad area 40 is disposed just adjacent to bottom and left sides of the non-display area 30.
In the display area 20, as shown in FIG. 2, a plurality of gate lines 22 and a plurality of data lines 26 are disposed on the substrate, respectively, in columns and rows. The gate lines 22 perpendicularly cross the data lines 26, thereby defining the pixels P in a matrix type. A pixel electrode 59 is disposed corresponding to each pixel P, and the thin film transistor T is disposed at a corner of the pixel P near the crossing of the gate and data lines 22 and 26. Each thin film transistor T includes a gate electrode (not shown) that extends from the gate line 22, a source electrode (not shown) that extends from the data line 26, and a drain electrode (not shown) that is connected with the pixel electrode 59.
The non-display area 30 is a region where a seal pattern is placed to attach the color filter substrate to the array substrate. Since the non-display area 30 does not include any pixels P, the non-display area 30 would be unable to show images when the array cell 10 is adopted in the liquid crystal display panel.
A plurality of gate pads 24 and a plurality of data pads 28 are disposed in the pad area 40. The plurality of gate pads 24 are connected with the plurality of gate lines 22, respectively, and disposed at the bottom portion of the pad area 40. In this same manner, the plurality of data pads 28 are connected with the plurality of data lines 22, respectively, and are disposed at the left portion of the pad area 40. Thus, the pad area 40 is divided into a gate pad area 42 where the gate pads 24 are placed, and a data pad area 44 where the data pads 28 are placed. The gate pads 24 and the data pads 28 act as connection terminals that electrically connect the gate and data lines 22 and 26 to the external driving circuits.
Still referring to FIGS. 1 and 2, the array substrate includes the plurality of array cells 10 and a plurality of test pads 50 each corresponding to each array cell 10. The array substrate also includes test lines 60 each connecting the test pad 50 to the corresponding array cell 10. The test pad 50 acts as an input terminal by way of receiving signals from the array testing apparatus during the array test.
In FIG. 1, the test pads 50 are generally disposed at top and bottom peripheries of the large array substrate. The test line 60 connects the test pad 50 to the gate and data pads 24 and 28 of the corresponding array cell 10 such that the test line 60 has a one-to-one connection between the test pad 50 and the array cell 10. Each test pad 50 includes at least one gate test pad 52 that is connected with the gate pads 24 of the array cell 10, and at least one data test pad 54 that is connected with the data pads 28. In this manner, the test line 60 is divided into a gate test line 62 that connects the plurality of gate pads 24 to the gate test pad 52 and a data test line 64 that connects the plurality of data pads 28 to the data test pad 54. These test pads 50 and test lines 60 can be formed together with the gate lines 22 and/or the data lines 26 in a same process step.
The array testing apparatus inspects the above-described array substrate by way of applying first and second voltages to the gate test pad 52 and data test pad 54, respectively. Thus, when the pixel electrodes 59 generate electric fields in the pixels P and the electric fields are converted into a light signal, the array testing apparatus perceives and analyzes the light signal and determines whether each pixel P is defective and whether the gate and data lines 22 and 26 are opened or broken. At this time of testing the array substrate using the array tester, the first voltage applied to the gate lines 22 throughout the gate test pad 52 becomes an ON/OFF voltage that turns on and off the thin film transistors T. The second voltage applied to the data line 26 through the data test pad 54 becomes a standard voltage that determines the degree of rotation of the liquid crystal molecules.
Meanwhile, after the array test, the array substrate is cut and divided into the array cells 10 along cutting lines S-Sxe2x80x2 as shown in FIG. 2. At this time, the test pads 50 and the test lines 60 are also removed by cutting along lines S-Sxe2x80x2 of FIG. 2. Actually, the test pads 50 and the test lines 60 are used only for the array test and do not play other roles. Thus, those test pads and lines 50 and 60 are required to be removed. Namely, when a scribing process cuts the large array substrate into each array cell 10 for making a liquid crystal display panel, the test pads and lines 50 and 60 are cut away from the array cells 10.
In order to scribe and cut the array substrate and divide into the array cells 10, the array cells 10 are spaced apart from one another and the corresponding test line 60 is placed in that space between two array cells 10. Namely, the array cells 10 are disposed on the large array substrate in up-and-down and left-and-right directions, and the test line 60 is placed in a space L1 between array cells 10 that are disposed in a row. The space L1 can be called an test line area where the test line 60 is placed. Further, the gate pad area 42 is usually disposed at the bottom of each array cell 10, and the data pad area 44 is disposed at the left side of each array cell 10, as shown in FIG. 2.
FIG. 2 shows the scribing process to form the individual array cell 10. Here, the first cutting line S1-S1xe2x80x2 corresponds to a left outer line of the pad area 40, the second cutting line S2-S2xe2x80x2 corresponds to a right outer line of the non-display area 30, the third cutting line S3-S3xe2x80x2 corresponds to a top outer line of the non-display area 30, and the fourth cutting line S4-S4xe2x80x2 corresponds to a bottom outer line of the pad area 40. Thus, since the array substrate is cut along the lines S-Sxe2x80x2, the test pads 50 and the test lines 60 are removed from the array cells 10.
However, the array substrate designed to be like FIG. 2 has some disadvantages. Since the spaces L1 are disposed among the horizontally arranged array cells 10 and the test lines 60 only used for the array test are placed in those spaces L1, the array cells 10 are spaced apart by the space L1. That is, the array cells 10 are ineffectively organized on the array substrate.
Accordingly, the present invention is directed to an array substrate for an LCD device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an array substrate maximizing spatial availability.
Another object of the present invention is to provide an array substrate having a improved spatial effectiveness.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a substrate having an array testing system for use in a liquid crystal display device comprises a plurality of array cells each including a display area, a non-display area surrounding the display area, and a pad area disposed adjacent to first and second sides of the non-display area; a plurality of test pads disposed outside the plurality of array cells; and a plurality of test lines each connecting a corresponding one of the array cells with a corresponding one of the test pads, each one of the test lines partially passing through the non-display area of an array cell adjacent to the corresponding one of the array cells.
In another aspect, a method of manufacturing a liquid crystal display device comprises the steps of forming a plurality of array cells on an array substrate, each array cell including a display area, a non-display area surrounding the display area, and a pad area disposed adjacent to first and second sides of the non-display area; forming a plurality of test pads on the array substrate each disposed outside the plurality of array cells; forming a plurality of test lines on the array substrate each connecting a corresponding one of the array cells with a corresponding one of the test pads, each one of the test lines partially passing through the non-display area of an array cell adjacent to the corresponding one of the array cells; testing the array substrate using the test pads and the test lines; and dividing the array substrate into individual array cells.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.